(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal-insulator-metal (MIM), capacitor structure as part of a process sequence used to also form copper damascene interconnect structures.
(2) Description of Prior Art
Capacitor structures exhibiting high reliability as well as low defect density, for use in high performance mixed signal and RF circuits, are formed via processes integrated with the processes used to fabricate complimentary metal oxide semiconductor (CMOS), devices. Metal-insulator-metal (MIM), capacitors are usually formed either before, simultaneously, or after, formation of copper interconnect structures, defined via damascene procedures. However several process issues encountered with copper damascene processing can adversely influence the yield and reliability of the MIM structures, formed during a copper damascene process sequence. First, the low dielectric constant (low k), materials used as intermetal dielectric (IMD), layers sometimes formed of polymer layers featuring poor dielectric quality, located surrounding copper damascene or MIM capacitor structures, can present unwanted leakage paths for the adjacent capacitor structures. Secondly, MIM capacitor structures formed directly as damascene structures have the top surface of the metal plate exposed to subsequent processing sequences, such as chemical mechanical polishing (CMP), procedures, which can result in a damaged MIM capacitor structure. In addition exposed edges of already defined MIM capacitor structures can be damaged during subsequent copper damascene fabrication procedures.
The present invention will describe a method of forming a MIM capacitor structure in a copper damascene process sequence, in which leaky structures resulting from etching of adjacent low k, IMD layers, or from etching of surrounding polymer layer, is eliminated. The present invention will also describe a method of forming an MIM capacitor structure in which the edges of the MIM capacitor structure are not damaged, nor is the top plate of the capacitor structure exposed, during subsequent process sequences. Prior art such as Jang et al, in U.S. Pat. No. 6,387,775 B1, Cook et al, in U.S. Pat. No. 6,001,702, Weng et al, in U.S. Pat. No. 5,946,567, and Chen, in U.S. Pat. No. 6,313,003 B1, describe methods of forming capacitor structures, as well as forming a capacitor structure using a damascene process. However none of these prior art describe the novel procedure used in this present invention wherein a MIM capacitor structure is successfully integrated into a copper damascene process sequence, featuring protection of specific elements of the MIM capacitor structure during subsequent copper damascene processing.